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<meta name="description" content="*This text is mostly lifted from the [Simulated Clock Generation](./verilog.html#clock) section of my Verilog Coding Standard. Credit goes to Claire Wolf ([@oe1cxw](https://twitter.com/oe1cxw)) for teaching me this finer point of Verilog simulation.*">
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<h1>Simulation Clock</h1>
<p><em>This text is mostly lifted from the <a href="./verilog.html#clock">Simulated Clock
 Generation</a> section of my Verilog Coding Standard.
 Credit goes to Claire Wolf (<a href="https://twitter.com/oe1cxw">@oe1cxw</a>) for
 teaching me this finer point of Verilog simulation.</em></p>
<p><strong>NOTE: This code cannot work in Verilator, which can only simulate
 synthesizable Verilog, and thus does not support delayed assignments.</strong>
 Simulate the clock in the C++ testbench instead, or if you must use
 Verilog, try the Icarus Verilog simulator.</p>
<p><strong>NOTE: This clock cannot be used directly as a periodic data signal.</strong> It
causes a race condition in the Verilog simulation event queue. I have not
yet found a solution.</p>
<p>In simulation, a race condition can exist at time zero between the initial
 value assignment of a register and the first clock edge. For example:</p>
<pre><code>reg clock = 1'b0; // Counts as a negedge at time zero! (1'bX -&gt; 1'b0)
reg foo   = 1'b0; // Also does 1'bX -&gt; 1'b0 at time zero.
reg bar   = 1'b0;

// Simulate the clock
always begin
    #HALF_PERIOD clock = ~clock;
end

// Use the simulated clock
always @(negedge clock) begin
    bar &lt;= foo;
end
</code></pre>
<p>In the code above, it is unclear if the initial negative clock edge or the
 initialization of <code>foo</code> will simulate first, so <code>bar</code> might get assigned
 1'bX for the first simulation cycle, which is not what the code intends.
 This race condition is another reason to only use <code>@(posedge clock)</code> in
 internal logic, but the same race condition will happen if the simulation
 clock happens to be initialized to 1'b1.</p>
<p>Instead, the following clock simulation idiom avoids the race condition by
 making use of undefined values and the identity operator <code>===</code>, which
 matches X values exactly, instead of the equality <code>==</code> operator which
 treats X as false: we leave the clock uninitialized to 1'bX, and compare it
 by identity after one clock half-period delay, which then assigns it false
 (1'b0).</p>

<pre>
`default_nettype none

`timescale 1ns / 1ps

module <a href="./Simulation_Clock.html">Simulation_Clock</a>
#(
    parameter CLOCK_PERIOD = 10
)
(
    output reg clock
);

    localparam HALF_PERIOD = CLOCK_PERIOD / 2;

    always begin
        #HALF_PERIOD clock = (clock === 1'b0);
    end

endmodule
</pre>

<p>Additionally, the following tidbits are handy to use with the resulting
 clock.  If you use <code>WAIT_CYCLES</code> or <code>UNTIL_CYCLE</code> exclusively to time
 actions, without using <code>#</code> delays, then a <code>timescale</code> directive is not
 necessary anywhere else, and your simulation will run at the correct
 simulated rate.</p>
<pre><code>`define WAIT_CYCLES(n) repeat (n) begin @(posedge clock); end

time cycle = 0;

always @(posedge clock) begin
    cycle = cycle + 1;
end

`define UNTIL_CYCLE(n) wait (cycle == n);
</code></pre>

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